https://zhangdoa.com/5d92b5... This picture helps me a lot. I am struggling learning D3D 12 now. Could you attach some references that you think great?

Hi zhangdoa , Thanks for your sharing! Is AMD Picasso UMA?
https://en.wikipedia.org/wi...

Take a look at HSA, AMD's APU should be UMA🤔😀.

Hi. Thanks for the article. I was trying to understand how D3D12 works with RAM and VRAM and your article was enlightening. But one thing is still not clear to me. In a NUMA architecture (with RAM and VRAM) a default buffer reside in VRAM. But where does an Upload Buffer reside? In RAM or VRAM?

Hi Judson Santiago, glad my article helps! Theoretically speaking, an upload buffer should reside inside a heap that allows the CPU write operation, and on a NUMA machine the D3D12_MEMORY_POOL_L0 (RAM) is typically the only pool that supports it, so we could say upload buffer would reside in RAM. Since I can't find a 100% clear statement that it's impossible to allow CPU to access VRAM directly (and typically it shouldn't be possible for the sake of physics), I've experimented to create a custom heap with D3D12_CPU_PAGE_PROPERTY_WRITE_COMBINE and D3D12_MEMORY_POOL_L1, and the validation layer thrown error as D3D12_CPU_PAGE_PROPERTY_NOT_AVAILABLE must be used with D3D12_MEMORY_POOL_L1. [ STATE_CREATION ERROR #638: CREATERESOURCEANDHEAP_INVALIDHEAPPROPERTIES]. So unfortunately, the attempt to create VRAM heap for the upload buffer is not possible at least on my GTX1070, but I've seen the possibility for upload buffer on VRAM at AMD's Vega, you could do some further experiments or investigations and draw the conclusion by yourself😀.

Awesome. I will investigate. Thanks.